## Master-Slave D Flip-Flop Design Using NAND Gates
## 1. Master Latch Design
Components Needed:
- 4 NAND gates
Functionality:
- The master latch captures the input (D) and holds it until a control signal (often a clock pulse) arrives.
Design Steps:
1. Latch Inputs Setup:
- Use two NAND gates to create a latch. Let's call them NAND1 and NAND2.
- NAND1 will control the latch's ability to latch new data, and NAND2 will control the holding of the current data.
2. NAND1 (Data Latch):
- Connect the D input directly to one input of NAND1.
- Connect the output of NAND2 to the other input of NAND1.
- The output of NAND1 becomes the output Q of the master latch.
Truth Table for NAND1:
```
D | Q (output)
----|-----------
0 | 1 (latched)
1 | 0 (latched)
```
3. NAND2 (Hold Latch):
- Use two more NAND gates to form NAND2.
- Connect the output of NAND1 (Q) to one input of NAND2.
- Connect the clock signal (CLK) to the other input of NAND2.
- The output of NAND2 becomes the output Q' of the master latch.
Truth Table for NAND2:
```
CLK | Q' (output)
----|------------
0 | 1 (hold)
1 | 0 (hold)
```
- When CLK = 0, the state of Q' remains held (latched).
- When CLK = 1, the state of Q' follows Q (latches the new value).
## 2. Slave Latch Design
Components Needed:
- 4 NAND gates
Functionality:
- The slave latch captures the value from the master latch only when enabled by the clock signal.
Design Steps:
1. Input Control:
- Use two NAND gates to form a control for the slave latch. Let's call them NAND3 and NAND4.
2. NAND3 (Control Logic):
- Connect the output Q' of the master latch to one input of NAND3.
- Connect the clock signal (CLK) to the other input of NAND3.
- The output of NAND3 will control the operation of the slave latch.
Truth Table for NAND3:
```
Q' | CLK | Control Output
---|-----|---------------
0 | 0 | 1 (enable)
0 | 1 | 1 (enable)
1 | 0 | 0 (disable)
1 | 1 | 1 (enable)
```
3. NAND4 (Slave Latch):
- Use two more NAND gates to form NAND4.
- Connect the D input directly to one input of NAND4.
- Connect the output of NAND3 to the other input of NAND4.
- The output of NAND4 becomes the output Q of the slave latch.
Truth Table for NAND4:
```
D | Control | Q (output)
---|---------|-----------
0 | 1 | 1 (previous state)
1 | 1 | 0 (new state)
```
- When NAND3 outputs 1 (enabled), NAND4 will latch the new value from D.
- When NAND3 outputs 0 (disabled), NAND4 will hold the previous state of Q.
## Complete Master-Slave D Flip-Flop
- Q (output): Comes directly from the output of NAND4 (slave latch).
- Q' (complement): Comes from the output of NAND2 (master latch).
## Summary
- Master latch (NAND1 and NAND2): Captures and holds input D based on the clock signal.
- Slave latch (NAND3 and NAND4): Transfers the latched value from the master latch to the output Q based on the clock signal.
This design effectively creates a master-slave D flip-flop using NAND gates, with clear control over the latching of input data (D) and its transfer to the output (Q) synchronized by a clock signal (CLK).
icDirectory United Kingdom | https://www.icdirectory.co.uk/a/blog/how-do-you-design-a-master-slave-d-flip-flop-using-nand-gates.html
