What is the UART data overrun error?
Technical Blog / Author: icDirectory United Kingdom / Date: Jun 24, 2024 02:06
A UART (Universal Asynchronous Receiver/Transmitter) data overrun error occurs when the UART receiver's buffer is full, and a new data byte arrives before the previous byte has been read. This means that the receive buffer is unable to store the new incoming data because it is still holding the previous data, resulting in data loss.

## Detailed Explanation of UART Data Overrun Error


## How UART Reception Works:


When data is transmitted over UART, it is received by the UART receiver bit by bit. The receiver assembles these bits into a complete data byte and stores this byte in a receive buffer (often a FIFO buffer or a single register). The CPU or an interrupt service routine (ISR) typically reads the data from this buffer and processes it.

## Causes of Overrun Errors:


1. Slow Processing: The CPU or ISR does not read the data from the receive buffer quickly enough, causing the buffer to overflow.
2. High Baud Rate: If the baud rate (data transmission speed) is very high, data bytes arrive more rapidly than they can be processed.
3. Insufficient Buffer Size: A small buffer size may not be sufficient to handle bursts of incoming data.
4. Interrupt Latency: Delays in servicing UART interrupts can prevent timely reading of the receive buffer.
5. System Load: High system load or other higher-priority tasks may preempt the process that reads data from the UART buffer, leading to delays.

## Detection of Overrun Errors:


UART hardware typically includes status registers with flags that indicate various error conditions, including overrun errors. When an overrun error occurs, the UART sets an overrun error flag in its status register to alert the software about the data loss.

## Consequences of Overrun Errors:


When an overrun error occurs, the newly arrived data byte is discarded because there is no space to store it. This results in data loss, which can be critical in applications requiring reliable data transmission.

## Handling Overrun Errors:


To handle and mitigate overrun errors, several strategies can be employed:

1. Increase Buffer Size: Using a larger receive buffer can help accommodate more incoming data and reduce the likelihood of overrun errors.
2. Optimize ISR Handling: Ensure that the interrupt service routine for UART reception is efficient and has a high priority, minimizing the time taken to read data from the receive buffer.
3. Flow Control: Implement hardware flow control (e.g., RTS/CTS) or software flow control (e.g., XON/XOFF) to manage the flow of data and prevent the sender from overwhelming the receiver.
4. Adjust Baud Rate: Lowering the baud rate can reduce the frequency of incoming data bytes, giving the receiver more time to process each byte.
5. DMA (Direct Memory Access): Using DMA can offload the data transfer task from the CPU, allowing faster and more efficient handling of incoming data.

## Example Handling in Embedded Systems:


In an embedded system, handling overrun errors involves checking the UART status register for the overrun error flag and implementing appropriate error recovery mechanisms. Here is a simple example in C:

```c
#define UART_STATUS_OVERRUN_ERROR (1

icDirectory United Kingdom | https://www.icdirectory.co.uk/a/blog/what-is-the-uart-data-overrun-error.html
Related Products
XR16C2852CJ-F
XR16C2852CJ-F
MaxLinear
Date: Jun 02, 2026
SC16C2550BIA44,512
SC16C2550BIA44,512
NXP Semiconductors
Date: Jun 01, 2026
XR16C2850CM-F
XR16C2850CM-F
MaxLinear
Date: Jun 01, 2026
XR16C2850IJTR-F
XR16C2850IJTR-F
MaxLinear
Date: Jun 01, 2026
SC16C2550IA44,529
SC16C2550IA44,529
NXP Semiconductors
Date: Jun 01, 2026
SC26C92A1A,529
SC26C92A1A,529
NXP Semiconductors
Date: Jun 01, 2026
XR16C2850CJ-F
XR16C2850CJ-F
MaxLinear
Date: Jun 01, 2026
SC26C92A1B,551
SC26C92A1B,551
NXP Semiconductors
Date: May 31, 2026
CS82C52Z
CS82C52Z
Renesas Electronics
Date: May 31, 2026
XR16C2550IJTR-F
XR16C2550IJTR-F
MaxLinear
Date: May 31, 2026
SC16C2550IA44,518
SC16C2550IA44,518
NXP Semiconductors
Date: May 31, 2026
ST16C1450CJ28TR-F
ST16C1450CJ28TR-F
MaxLinear
Date: May 31, 2026
Technical Blog
  • What is the UART data format?
  • What is the UART data framing error?
  • What is the role of start and stop bits in UART?
  • What is the UART overrun error?
  • How do you calculate the UART baud rate?
  • What is the UART communication data parity bit usage?
  • What is the baud rate in UART communication?
  • What is the UART communication reliability?
  • What is the UART communication data buffering strategy?
  • How do you troubleshoot UART communication issues?
  • What is the UART communication handshaking?
  • What is the UART communication master-slave mode?
  • What is the UART communication data stop bit duration?
  • What is the UART communication data integrity check?
  • What is the UART communication multipoint mode?
  • What is the UART communication flow control?
  • How do you configure UART communication?
  • What is the UART communication distance?
  • What is the UART idle line condition?
  • What is the UART communication data word length configuration?
  • What is the UART communication data multiplexing technique?
  • What is the UART break condition?
  • What is the UART communication full-duplex mode?
  • What are the disadvantages of UART communication?
  • What is the UART communication data error detection mechanism?
  • What is the UART communication data framing format?
  • What is the UART communication data integrity?
  • What is the UART data idle line condition?
  • What is the maximum cable length for UART communication?
  • What is the UART stop bit?