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How many TSN-enabled Ethernet ports are supported in the HPS of the Altera Agilex 5 FPGA SoCs?
Technical Blog / Author: icDirectory United Kingdom / Date: Apr 15, 2026 11:04

## HPS Architecture and Ethernet Integration in Agilex 5 SoCs


The Hard Processor System (HPS) in Altera (Intel) Agilex 5 SoC FPGAs features a heterogeneous quad-core Arm processor cluster (dual Cortex-A76 at up to 1.8 GHz and dual Cortex-A55 at up to 1.5 GHz) with a shared 2 MB L3 cache, multi-channel DMA controllers, 512 KB on-chip SRAM, and a comprehensive set of hardened peripherals. This subsystem is tightly coupled to the FPGA fabric through AXI bridges, lightweight bridges, and direct memory access paths, enabling efficient control-plane and real-time processing alongside high-performance FPGA acceleration. The HPS I/O subsystem includes dedicated multiplexed I/O (MIO) pins and routing options to HSIO/HVIO banks, allowing flexible interfacing to external components while maintaining low-latency access to peripherals.

Ethernet connectivity within the HPS is implemented through dedicated hardened Media Access Controllers (MACs) that are fully integrated into the HPS peripheral complex. These MACs are distinct from the higher-speed GTS transceiver-based hardened Ethernet IP blocks available in the FPGA fabric (which support 10/25 GbE with PCS/FEC). The HPS Ethernet MACs are optimized for embedded control, management traffic, and deterministic networking applications, with native support for Time-Sensitive Networking (TSN) features.

## Number of TSN-Enabled Ethernet Ports in the HPS


The HPS in all Agilex 5 SoC variants supports three TSN-enabled Ethernet MACs. These are consistently listed across official product tables, device overviews, and technical reference materials as "TSN MAC x3". Each MAC is a hardened instance capable of independent operation, providing up to three simultaneous TSN-enabled Ethernet ports directly from the HPS. This configuration is uniform for both E-Series and D-Series SoC devices, including the highest-density variants such as A5E 065 and A5D 064, and applies regardless of Group A or Group B speed grades.

These three MACs support data rates of 10/100/1000 Mbps (1 GbE) and 2.5 Gbps (2.5 GbE), with configurable interfaces including RGMII (Reduced Gigabit Media Independent Interface), SGMII (Serial Gigabit Media Independent Interface), and GMII (Gigabit Media Independent Interface) where appropriate. The MACs include integrated DMA engines for efficient packet transfer to/from system memory or the FPGA fabric, and they connect to external PHYs via MIO pins or through FPGA I/O routing when needed.

## Detailed TSN Features Supported by the HPS Ethernet MACs


Each of the three HPS Ethernet MACs implements comprehensive TSN endpoint functionality compliant with key IEEE standards, enabling deterministic, low-latency, and synchronized networking critical for industrial automation, automotive, robotics, and real-time control systems:

- IEEE 802.1AS-2020 (gPTP) for precise timing and synchronization, with hardware timestamping on transmit and receive paths achieving sub-microsecond accuracy.
- IEEE 802.1Qav (Credit-Based Shaper) for traffic scheduling and bandwidth allocation.
- IEEE 802.1Qbv (Time-Aware Shaper) for scheduled gate control lists and time-triggered traffic.
- IEEE 802.1Qbu (Frame Preemption) with support for express and preemptable MACs (eMAC/pMAC) and IEEE 802.3br interspersing.
- IEEE 1588v2 Precision Time Protocol (PTP) enhancements, including transparent clock support and correction field handling.
- Additional features such as VLAN tagging (802.1Q), priority-based flow control, and statistics counters for monitoring.

These TSN capabilities are hardened in silicon, minimizing fabric resource usage and ensuring low, deterministic latency even under heavy load. Example designs demonstrate configurations such as 3× 2.5G ports via SGMII/XCVR or RGMII interfaces, with full TSN feature sets active across all three ports simultaneously.

## Interface Options and System Integration


The three TSN MACs offer flexible physical interfacing:
- RGMII: Standard 4-bit DDR interface for 1/2.5 GbE connections to external PHYs, commonly used in cost-sensitive designs.
- SGMII: Serial interface leveraging transceiver resources or soft SERDES for 1/2.5 GbE.
- GMII: Parallel interface options for higher compatibility.

Pins can be multiplexed to HPS MIO or routed through FPGA I/O banks, with up to three independent PHY connections possible. In Linux environments (via the GSRD and device tree configurations), the MACs appear as separate network interfaces (e.g., eth0, eth1, eth2), with full support for TSN tools such as tc (traffic control) for gate scheduling and ethtool for configuration. Bare-metal or RTOS implementations can access the MACs directly through register maps and DMA descriptors.

Integration with the rest of the HPS includes shared access to the Arm interconnect, DMA channels for zero-copy transfers, and synchronization with the processor cores and FPGA fabric. The MACs can also interoperate with the higher-speed GTS-based Ethernet Hard IP (up to 6+ instances of 10/25 GbE) for hybrid high-bandwidth/data-plane and deterministic/control-plane architectures.

## Comparison with Fabric Ethernet and Previous Generations


Unlike the fabric-based GTS Ethernet Hard IP (which focuses on 10/25 GbE with PCS/FEC for high-throughput applications), the HPS MACs emphasize TSN determinism at lower-to-mid speeds with integrated processor offload. This complements the overall device by allowing the HPS to handle control and synchronization while the fabric manages packet processing or acceleration.

Compared to previous generations:
- Arria 10 and Stratix 10 SoCs offered fewer or less capable Ethernet MACs with limited or soft TSN support.
- Agilex 5 introduces full hardened TSN across all three MACs, representing a significant upgrade in deterministic networking capabilities.

## Practical Design and Software Considerations


In system design, engineers allocate the three TSN ports for applications such as multi-axis motion control, synchronized sensor networks, or redundant industrial links. Power domains for the HPS Ethernet MACs are shared with the processor complex, requiring careful PDN design for simultaneous full-rate operation. Quartus Prime Pro and the SoC Embedded Design Suite provide configuration wizards, device tree templates, and example designs (including TSN RGMII, TSN SGMII, and multi-port setups) for rapid development.

Linux kernel drivers (stmmac-based) fully expose TSN features, with U-Boot and Arm Trusted Firmware supporting boot-time initialization. Performance characterization shows line-rate operation with TSN scheduling overhead kept minimal due to hardware acceleration. All three ports can operate concurrently with independent PTP domains or synchronized timing.

This three-port TSN configuration, combined with the rich HPS peripheral set (USB 3.1, I2C/I3C, SPI, UART, etc.), makes Agilex 5 SoCs highly suitable for edge computing, industrial IoT, and real-time embedded systems. All details are consistent with official Intel/Altera product tables, device overviews, HPS Technical Reference Manuals, and validated example designs.

icDirectory United Kingdom | https://www.icdirectory.co.uk/a/blog/how-many-tsn-enabled-ethernet-ports-are-supported-in-the-hps-of-the-altera-agilex-5-fpga-socs.html
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